Currently, DRAM memory devices have reached the limits of improving integration 
density due to challenges in controlling leakage currents in insulating films at 
design rules below 10 nm and process issues related to high aspect ratio capacitors. 
As a result, research is being conducted on stacked 3D DRAM that employs 
horizontal capacitors to overcome these limitations. In this work, we plan to 
fabricate 3D vertical two-layer oxide semiconductor TFT devices based on an AAC 
structure that do not require capacitors, which are essential in conventional DRAM. 
This approach will enable us to secure the fundamental technologies for oxide 
semiconductor channel-based 2T DRAM nano devices. In addition, we will discuss 
current research on STT& SOT-MRAM (Spin-transfer & Orbit Torque 
Magnetoresistive Random-Access Memory), which is securing the fundamental 
technologies related to materials, processes, and device structures for a novel 
skyrmion-based two-terminal, STT & SOT-MRAM.